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Attack Patterns CAPEC-674 — Design for FPGA Maliciously Altered
CAPEC-674

Design for FPGA Maliciously Altered

TLP:CLEAR

Description

Typical severity: High. Likelihood of attack: Low. An adversary alters the functionality of a field-programmable gate array (FPGA) by causing an FPGA configuration memory chip reload in order to introduce a malicious function that could result in the FPGA performing or enabling malicious functions on a host system. Prior to the memory chip reload, the adversary alters the program for the FPGA by adding a function to impact system operation.

Mitigation

Utilize DMEA’s (Defense Microelectronics Activity) Trusted Foundry Program members for acquisition of microelectronic components. | Ensure that each supplier performing hardware development implements comprehensive, security-focused configuration management including for FPGA programming and program uploads to FPGA chips. | Require that provenance of COTS microelectronic components be known whenever procured. | Conduct detailed vendor assessment before acquiring COTS hardware.

Details

Platforms
Supply-chain
Hardware
Added
Jul 14, 2026
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